ESD protection of I/O pins at sub-nanometer scaling becomes difficult. On the one hand, low voltage I/O cannot simply be protected by a snapback device due to the triggering voltage levels of snapback devices. On the other hand, the use of active clamp circuits (e.g. Merrill clamps that use gate control to switch on) for providing ESD protection is also difficult at the extremely low absolute maximum voltages of low voltage devices. In addition active clamps are large and use up a lot of chip area.
One approach has been to make use of diode chains where there is sufficient isolation, however the high on-state resistance and temperature coefficient makes the use of diodes unattractive for high ESD current.
The invention seeks to provide another solution to the problem of low reference voltage ESD protection.